1. Field of the Invention
The present invention relates to a D/A conversion circuit for converting a digital signal into an analog signal, and particularly, to a D/A conversion circuit used in a driving circuit of a semiconductor display device.
2. Description of the Related Art
In recent years, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, such as a thin film transistor (TFT), has been rapidly developed. The reason is that a demand for an active matrix type semiconductor display device (particularly, an active matrix type liquid crystal display device) has been increased.
The active matrix type liquid crystal display device is structured such that a TFT is disposed for each of several tens to several millions of pixel regions disposed in matrix, and an electric charge going in and out of respective pixel electrodes is controlled by the switching function of the TFT.
Among them, with the improvement of fineness and picture quality of a display device, attention comes to be paid to a digital driving system active matrix type liquid crystal display device capable of being driven at high speed.
FIG. 31 shows a conventional digital driving system active matrix type liquid crystal display device. As shown in FIG. 31, the conventional digital driving system active matrix type liquid crystal display device includes a source signal line side shift register 01, address lines 02 of a digital decoder, latch circuits 03 (LAT1), latch circuits 04 (LAT2), a latch pulse line 05, D/A conversion circuits (digital/analog conversion circuits) 06, source signal lines 07, a gate signal line side shift register 08, gate signal lines (scanning lines) 09, pixel TFTs 10, and the like. Here, the 2-bit digital driving system active matrix type liquid crystal display device is taken for instance. Incidentally, in the latch circuits LAT1 and LAT2, respectively, two latch circuits are shown in one bundle for convenience.
Digital gradation signals supplied to address lines 02 (1 and 2) of the digital decoder are written in the LAT1 group by timing signals from the source signal line side shift register 01.
A time in which writing of the digital gradation signals into the LAT1 group is roughly completed, is referred to as one line period. That is, one line period is a time interval between the start point of writing of a gradation signal from the digital decoder into the leftmost LAT1 and the end point of writing of a gradation signal from the digital decoder into the rightmost LAT1.
After the writing of the gradation signals into the LAT1 group is completed, when a latch pulse flows to the latch pulse line 05 synchronously with the operation timing of the shift register, the gradation signals written in the latch 1 group are transmitted all at once into the LAT2 group and are written.
Into the LAT1 group which have finished transmission of the gradation signals into the LAT2 group, writing of gradation signals supplied to the digital decoder is again sequentially carried out by a signal from the source signal line side shift register 01.
In the second one line period, according to the gradation signals transmitted to the LAT2 group synchronously with the start of the second one line period, one of four gradation voltages is selected by the D/A conversion circuits 06.
The selected gradation voltage is supplied to the corresponding source signal line in one line period.
By repeating the above-mentioned operation, images are supplied to the entire pixel portion of the liquid crystal display device.
Here, the conventional D/A conversion circuit used in the foregoing driving circuit will be described.
FIG. 32 shows the D/A conversion circuit 06 of the foregoing active matrix type liquid crystal display device. As shown in FIG. 32, the D/A conversion circuit 06 is made up of four NAND circuits 22.1 to 22.4, four gradation voltage lines (V0 to V3) 23, and four P-channel TFTs 24.1 to 24.4.
Such a structure is adopted that one of the four P-channel TFTs 24.1 to 24.4 is selected according to signals supplied from the LAT2 group to signal lines 21a and 21b and their inversion signals. Then a voltage is applied to the source signal line 07 from the gradation voltage line connected to the selected TFT.
A circuit pattern diagram and a circuit diagram of the NAND circuit 22 of the above D/A conversion circuit 06 are shown in FIGS. 33A and 33B, respectively. In FIG. 33A, wiring lines having the same pattern indicate the same wiring layers. Reference numerals 33, 34 and 38 denote gate electrode wiring layers, and 35 to 37 denote second wiring layers formed over the gate electrode wiring layers with an insulating layer interposed therebetween.
Reference numeral 31 denotes a semiconductor active layer of a P-channel TFT, and 32 denotes a semiconductor active layer of an N-channel TFT. Reference numerals 33 and 34 denote gate electrode wiring lines, and form TFTs Tr1 and Tr4, and TFTs Tr2 and Tr3, respectively. An input signal Vin1 is inputted to the gate electrode wiring line 34, and an input signal Vin2 is inputted to the gate electrode wiring line 33. Reference numeral 35 denotes a wiring line for supplying a voltage from Vdd, which is connected to source regions of the TFTs Tr1 and Tr2. The second wiring layer 36 is connected to drain regions of the TFTs Tr1 and Tr2 and a drain region of the TFT Tr3, and supplies an output signal to the gate electrode wiring layer 38 Vout. The second wiring layer 37 denotes a GND wiring line, and is connected to a source region of the TFT Tr4. Blackened portions 39 indicate portions where the semiconductor active layer is connected to the second wiring layer, or the gate electrode wiring layer is connected to the second wiring layer.
FIG. 33B shows an equivalent circuit of the circuit pattern of the NAND circuit of the D/A conversion circuit shown in FIG. 33A.
According to FIGS. 33A and 33B, in the NAND circuit, there are many (five) portions (typically denoted by reference numeral 40) where the second wiring layer is connected to the semiconductor active layer or the gate electrode wiring layer. In these connection portions, in order to compensate a shift which occurs at the time of making a contact hole for the above connection, the semiconductor active layer must be made large more than needs. Thus, there is a defect that the whole area of the circuit becomes large.
In the foregoing 2-bit D/A conversion circuit, four such NAND circuits are required. Moreover, in the whole driving circuit, the number of required D/A conversion circuits is equal to the number of source signal lines. As a result, the rate of the area of the D/A conversion circuits (NAND circuits) occupying the driving circuit becomes large. This is one of causes of hindering the miniaturization of a semiconductor display device.
In order to improve the fineness of the semiconductor display device, it becomes necessary to increase the number of pixels, that is, the number of source signal lines. However, as described above, one D/A conversion circuit is necessary for one signal line, which is one of causes of hindering the improvement in the fineness.
FIG. 34 shows another conventional digital driving system active matrix type liquid crystal display device. As shown in FIG. 34, the conventional digital driving system active matrix type liquid crystal display device includes a source signal line side shift register 51, address lines (a to d) 52 of a digital decoder, latch circuits (LAT1) 53, latch circuits (LAT2) 54, a latch pulse line 55, D/A conversion circuits 56, gradation voltage lines 57, source signal lines 58, a gate signal line side shift register 59, gate signal lines (scanning lines) 60, pixel TFTs 61, and the like. Here, the 4-bit digital driving system active matrix type liquid crystal display device is taken for instance. Incidentally, in the latch circuits LAT1 and LAT2, respectively, four latch circuits are shown in one bundle for convenience.
Digital signals (digital gradation signals) supplied to the address lines (a to d) 52 of the digital decoder are sequentially written in the LAT1 group by timing signals from the source signal line side shift register 51.
A time in which writing of the digital signals into the LAT1 group is roughly completed, is referred to as one line period. That is, one line period is a time interval between the start point of writing of a digital signal from the digital decoder into the leftmost LAT153 and the end point of writing of a digital signal from the digital decoder into the rightmost LAT1.
After the writing of the digital signals into the LAT1 group is completed, when a latch pulse flows to the latch pulse line 55 synchronously with the operation timing of the shift register, the digital signals written in the latch 1 group are transmitted all at once into the LAT2 group and are written.
Into the LAT1 group which have finished transmission of the digital signals into the LAT2 group, writing of digital signals supplied to the digital decoder is again sequentially carried out by signals from the source signal line side shift register 51.
In the second one line period, voltages corresponding to the digital signals transmitted to the LAT2 group are supplied to the source signal lines 58 synchronously with the start of the second one line period. In the driving circuit quoted as an example here, conversion of a digital signal into a gradation voltage is carried out in such a manner that the D/A conversion circuit 56 selects one of 16 gradation voltages.
The selected gradation voltage is supplied to the corresponding source signal line 58 in one line period. By a scanning signal from the gate signal line side shift register 59, switching of a corresponding TFT is carried out and liquid crystal molecules are driven.
One picture (one frame) is formed by repeating the above-mentioned operation a certain number of times, the number being equal to the number of scanning lines. In general, in an active matrix type liquid crystal display device, renewal of pictures of 60 frames a second is carried out.
Here, the conventional D/A conversion circuit 56 used in the foregoing digital driving circuit will be described in FIG. 35.
The conventional 4-bit D/A conversion circuit includes a plurality of switches (sw0 to sw15) and gradation voltage lines (V0 to V15). This circuit is designed such that one of the plurality of switches (sw0 to sw15) is selected by a 4-bit digital signal supplied from the LAT2 group, and a voltage is supplied to the source signal line 58 from the gradation voltage line 57 connected to the selected switch.
Such a D/A conversion circuit 56 is provided for one source signal line 58 in a one-to-one correspondence.
In the case of the conventional 4-bit D/A conversion circuit 56 described here, the number of switches is 16, and the number of gradation voltage lines 57 is 16. In an actual active matrix type liquid crystal display device, the area of a switch is large and the total area of the driving circuit becomes large.
Here, another example of a conventional 4-bit D/A conversion circuit will be described in FIG. 36. Similarly to the 4-bit D/A conversion circuit described before, the 4-bit D/A conversion circuit shown in FIG. 36 is designed such that one of a plurality of switches (sw0 to sw15) is selected by a 4-bit digital signal supplied from the LAT2 group, and a voltage is supplied to the source signal line from the gradation voltage line connected to the selected switch.
In the D/A conversion circuit shown in FIG. 36, the number of gradation voltage lines is 5 (V0 to V4), which is smaller than that of the previously described 4-bit D/A conversion circuit as shown in FIG. 35. However, the number of switches is 16. Thus, the total area of the driving circuit can not be reduced.
Although the D/A conversion circuit which processes a 4-bit digital signal is described here, if the number of bits is increased, the number of switches is increased exponentially. That is, in a conventional D/A conversion circuit which processes an n-bit digital signal, 2n switches are required. Thus, the area of a driving circuit becomes large.
The largeness of the driving circuit as described above is one of causes of hindering the miniaturization of a semiconductor display device, particularly an active matrix type liquid crystal display device.
Moreover, for the purpose of improving the fineness of a semiconductor display device, it becomes necessary to increase the number of pixels, that is, the number of source signal lines. However, as described above, if the number of source signal lines is increased, the number of D/A conversion circuits is also increased and the area of the driving circuit is increased, which is one of causes of hindering the improvement of fineness.
From the reasons described above, a D/A conversion circuit with a small area has been earnestly desired.
The present invention has been made in view of the foregoing problems, and an object thereof is to provide a D/A conversion circuit small in area.
According to an aspect of the present invention, in a D/A conversion circuit in which one of 2n gradation voltage lines is selected according to an inputted n-bit (n is an integer not less than 2) digital signal and a gradation voltage is supplied to an output line from the selected gradation voltage line, a first circuit including n P-channel TFTs connected in series to each other is connected in series to a second circuit including n N-channel TFTs connected in series to each other, a circuit including the first circuit and the second circuit is connected in parallel to each of the 2n gradation voltage lines, a connection portion between the first circuit and the second circuit is connected to the output line, and the digital signal switches the n P-channel TFTs and the n N-channel TFTs connected to each of the 2n gradation voltage lines. The above object is achieved by this structure.
The n P-channel TFTs may be connected each other through only a semiconductor layer, and the n N-channel TFTs may be connected each other through only a semiconductor layer.
The D/A conversion circuit may be formed over an insulating substrate.
According to another aspect of the present invention, in a D/A conversion circuit in which one of 2n gradation voltage lines is selected according to an inputted n-bit (n is an integer not less than 2) digital signal and a gradation voltage is supplied to an output line from the selected gradation voltage line, a first circuit including n P-channel TFTs connected in series to each other is connected in series to a second circuit including n N-channel TFTs, a circuit including the first circuit and the second circuit is connected in parallel to each of the 2n gradation voltage lines, a connection portion between the first circuit and the second circuit is connected to the output line, and the digital signal is supplied to gate electrodes of the n P-channel TFTs and gate electrodes of the n N-channel TFTs connected to each of the 2n gradation voltage lines. The above object is achieved by this structure.
The n P-channel TFTs may be connected each other through only a semiconductor layer, and the n N-channel TFTs may be connected each other through only a semiconductor layer.
The D/A conversion circuit may be formed on an insulating substrate.
According to still another aspect of the present invention, in a D/A conversion circuit in which one of 2n gradation voltage lines is selected according to an inputted n-bit (n is an integer not less than 2) digital signal and a gradation voltage is supplied to an output line from the selected gradation voltage line, a first circuit including n P-channel TFTs connected in series to each other is connected in series to a second circuit including n N-channel TFTs connected in series to each other, a circuit including the first circuit and the second circuit is connected in parallel to each of the 2n gradation voltage lines, voltages supplied to the 2n gradation voltage lines become high in a direction from the first gradation voltage line to 2n-th gradation voltage line, the x-th (1xe2x89xa6xxe2x89xa62n; x is an integer) gradation voltage line and the (2n+1xe2x88x92x)-th gradation voltage line are paired and are adjacent to each other, the arrangements of the first circuit and the second circuit in the paired gradation voltage lines are reverse to each other, a connection portion between the first circuit and the second circuit is connected to the output line, and the digital signal is supplied to gate electrodes of the n P-channel TFTs and gate electrodes of the n N-channel TFTs connected to each of the 2n gradation voltage lines. The above object is achieved by this structure.
The n P-channel TFTs may be connected each other through only a semiconductor layer, and the n N-channel TFTs may be connected each other through only a semiconductor layer.
The D/A conversion circuit may be formed over an insulating substrate.
According to still another aspect of the present invention, a D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line, characterized in that: the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n; each of x and y is a natural number); two adjacent gradation voltage lines are selected from the (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal; 2y gradation voltages are formed from gradation voltages of the two selected adjacent gradation voltage lines; and a corresponding gradation voltage in the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal. The above object is achieved by this structure.
The D/A conversion circuit may be formed by using thin film transistors over an insulating substrate.
According to still another aspect of the present invention, a D/A conversion circuit in which a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal is supplied to an output line, characterized in that: the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n; each of x and y is a natural number); a z-th gradation voltage line and a (z+1)-th gradation voltage line (1xe2x89xa6zxe2x89xa62x; z is a natural number) are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line; 2y gradation voltage lines are formed from gradation voltages of the selected z-th and (z+1)-th gradation voltage lines; and a corresponding gradation voltage in the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal. The above object is achieved by this structure.
The D/A conversion circuit may be formed by using thin film transistors over an insulating substrate.
According to still another aspect of the present invention, a semiconductor device comprises a plurality of TFTs disposed in matrix; and a source signal line side driving circuit and a gate signal line side driving circuit for driving the plurality of TFTs; and is characterized in that the source signal line side driving circuit includes a D/A conversion circuit which supplies a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal to an output line; the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n; each of x and y is a natural number); two adjacent gradation voltage lines are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal; 2y gradation voltages are formed from gradation voltages of the two selected adjacent gradation voltage lines; and a corresponding gradation voltage in the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal. The above object is achieved by this structure.
According to still another aspect of the present invention, a semiconductor device comprises a plurality of TFTs disposed in matrix; and a source signal line side driving circuit and a gate signal line side driving circuit for driving the plurality of TFTs; and is characterized in that the source signal line side driving circuit includes a D/A conversion circuit which supplies a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal to an output line; the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n; each of x and y is a natural number); a z-th gradation voltage line and a (z+1)-th gradation voltage line (1xe2x89xa6zxe2x89xa62x; z is a natural number) are selected from the (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line; 2y gradation voltages are formed from gradation voltages of the selected z-th and (z+1)-th gradation voltage lines; and a corresponding gradation voltage in the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal. The above object is achieved by this structure.
According to still another aspect of the present invention, a semiconductor device comprises a plurality of TFTs; and a source signal line side driving circuit and a gate signal line side driving circuit for driving the plurality of TFTs; and is characterized in that the source signal line side driving circuit includes a D/A conversion circuit which supplies a gradation voltage corresponding to an inputted n-bit (n is a natural number not less than 2) digital signal to an output line; the n-bit digital signal is divided into upper x bits and lower y bits (x+y=n; each of x and y is a natural number); a z-th gradation voltage line and a (z+1)-th gradation voltage line (1xe2x89xa6zxe2x89xa62x; z is a natural number) are selected from (2x+1) gradation voltage lines by the upper x bits of the n-bit digital signal, voltages supplied to the gradation voltage lines becoming high in a direction from the first gradation voltage line to the (2x+1)-th gradation voltage line; 2y gradation voltages are formed from gradation voltages of the selected z-th and (z+1)-th gradation voltage lines; and a corresponding gradation voltage in the 2y gradation voltages is supplied to the output line by the lower y bits of the n-bit digital signal. The above object is achieved by this structure.
The plurality of TFTs, the source signal line side driving circuit, and the gate signal line side driving circuit may be integrally formed by using thin film transistors on an insulating substrate.
A black mask (BM) layer of the semiconductor device may be made of an Al film, or a lamination film of Al and Ti.